1. Field of the Invention
This invention relates generally to computer readable memory devices, and, more specifically, to methods for reducing noise when reading their information content.
2. Background Information
In non-volatile semiconductor memories, such as EEPROMs, the amount of data stored per memory cell has been increased in order to increase storage densities. At the same time, the operating voltages of such devices have decreased to reduce power consumption. This results in a greater number states stored in a smaller range of voltage or current values. As the voltage or current separation between data states decreases, the effects of noise become more significant in the reading of these cells. For example, variations in the threshold value acceptable in a binary storage, 5 volts EEPROM cell may no longer be acceptable in a device operating at 3 volts with four or more bits storable per cell. Some consequences of noise, and methods for dealing with it, in a nonvolatile memory are described in U.S. Pat. No. 6,044,019, which is hereby incorporated by reference.
An example of noisy behaviour is shown in FIG. 1A, which is adapted from U.S. Pat. No. 6,044,019. This figure shows the variation in the current flowing through a memory cell in response to a particular set of bias conditions. The current fluctuates by an amount xcex94I due to various noise effects in the memory cell and interfacing circuitry. If, for example, the memory circuit works by current sensing, as the separation between states approaches xcex94I, the noise will begin to produce erroneous read values. Although the consequences of noise can be decreased by integration sensing techniques, such as those in U.S. Pat. No. 6,044,019, or treated with error correction code (ECC) or other equivalent error management, such as is described in U.S. Pat. No. 5,418,752, which is hereby incorporated herein by this reference, memories could benefit from further methods to reduce the effects of noise on memory operation.
The present invention presents methods to further reduce the effects of noise in non-volatile memories, thereby allowing the system to store more states per storage element in circuits where noise and other transients are a significant factor. The storage elements are read multiple times by sensing a parameter indicative of their state. The results are accumulated and averaged for each storage element to reduce the effects of noise in the circuits as well as other transients that may adversely affect the quality of the read.
The methods of the present invention can be implemented through several techniques. In a first set of embodiments, a full read and transfer of the data from the storage device to the controller device is performed for each iteration, with averaging performed by the controller. In a second set of embodiments, a full read of the data for each interruption is performed, but the averaging is performed within the storage device and no transfer of data to the controller takes place until the final results are sent. A third set of embodiments perform one full read followed by a number of faster re-reads by exploiting the already established state information to avoid a full read, with some intelligent algorithm to guide the state at which the storage element is sensed. This technique may be used as the normal mode of operation, or invoked upon exception condition, depending on the system characteristics.
A similar form of signal averaging may be employed during the verify phase of programming. An exemplary embodiment of this technique would use a peak-detection scheme. In this scenario, several verify checks are performed at the target state prior to deciding if the storage element has reached the final state. If some predetermined portion of the verifies fail, the storage element receives additional programming.